Multi-Gigahertz Source Synchronous Testing of an Optical Packet Switching Network

A programmable FPGA-based digital logic circuit is enhanced with high-speed, positive emitter-coupled logic (PECL) to create a standalone tester for a self routing optical packet switching network. This tester serves as a test bed for evaluating high-speed electrical to optical conversion techniques and the difficulties associated with burst packet transmissions across the switching network. The demonstration system supports a four-bit wide bus at 2.5-4Gbps per channel. With wavelength-divisionmultiplexing (WDM) the bit-parallel message width is extendible to hundreds of channels. The project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while positive emitter-coupled logic achieves multi-gigahertz data rates with about +25ps timing accuracy.